Academician Gennady Krasnikov, the President of the Russian Academy of Sciences, delivered a long-term vision for the advancement of the country’s microelectronics industry through 2042 at the Microelectronics 2026 forum in Russia. One of the most noteworthy aspects of his presentation was the potential for Russia to develop advanced semiconductor manufacturing processes.
According to Krasnikov, Russia has the potential to develop its own 28 nm semiconductor manufacturing technology by 2030–2031, provided that the appropriate level of funding is maintained. In his opinion, the nation could transition to 14nm technology approximately two years later. Russia has the potential to achieve process technology of approximately 2 nm by 2040 in the long term.
Nevertheless, the current state of Russian microelectronics and 28nm production are separated by a substantial technological and financial gap. The challenge extends beyond the construction of a single advanced fabrication facility. Additionally, Russia would be required to develop virtually the entire production chain, including semiconductor equipment, materials, chip design, and packaging itself.
Global Microelectronics Is Approaching Physical Limits
The global semiconductor industry is increasingly encountering fundamental limitations to conventional scaling, according to the president of the Russian Academy of Sciences. The primary method of improving the performance of integrated circuits for decades was to reduce the size of transistors. The industry was able to achieve 28 nm and 22 nm processes as a result of planar transistor technology. Subsequently, the industry began switching to three-dimensional FinFET transistors.
The FinFET architecture facilitated additional scaling into the 22nm-to-5nm and 3 nm ranges. At the same time, the process-node designation itself is no longer a direct indication of the physical dimensions of individual components. For specialists, what matters much more is the combination of technological solutions used to achieve the required characteristics of a chip.
The next major stage is Gate-All-Around, or GAA, architecture based on nanosheet transistors. In this design, the gate almost completely surrounds the transistor channel, providing much more effective control over its operation while also enabling lower power consumption.
The global semiconductor industry is anticipated to develop 2nm and 1.4nm processes based on nanosheet architecture between 2025 and 2028, as indicated by the roadmap provided. It is anticipated that the industry will transition to CFET technology at the start of the next decade. This technology involves the vertical stacking of n-type and p-type transistors. This architecture has the potential to facilitate further scalability below the 1 nm level.
Resistance, Heat, and Quantum Effects Become Major Problems
In addition to technological constraints, transistor scaling is constrained by fundamental physical constraints. The network of interconnections within a semiconductor is one of the most significant obstacles.
The electrical resistance of conductors increases as they become smaller. At the same time, the distance between components decreases, increasing parasitic capacitance. This results in RC delay, which is the product of capacitance and resistance that governs the speed at which signals can travel the circuit. A proportional increase in performance is no longer automatically achieved by merely shrinking transistors beyond a certain threshold.
Another major challenge is heat generation. The power density increases as the number of transistors that can be positioned on a given area increases. As a result, the removal of heat becomes a separate engineering challenge, which steadily restricts the potential for further increases in computing capacity.
Quantum effects also become increasingly significant at extremely small dimensions. Tunneling between the source and drain may occur when the transistor channel reaches dimensions at which the wave-like properties of electrons become significant. Consequently, the transistor’s capacity to regulate the passage of charge diminishes over time.
What will replace traditional technologies and copper?
New materials and methods of interconnect formation are currently being investigated by the global semiconductor industry in order to overcome these constraints. These consist of alternative metallization methods, new metallic materials, and low-K and high-K dielectrics.
Technologies such as semi-damascene and subtractive metallization are expected to become more significant at process levels of 1nm and below. Ruthenium, for instance, is being investigated as an alternative to copper. In an effort to mitigate parasitic effects and electrical resistance, self-aligned vias and air gaps are also being implemented.
At even more advanced levels, such as those around 0.5 nm and below, the necessity for altogether new materials and structures may arise. This illustrates the increasing complexity of each next stage of miniaturization. The semiconductor industry of the present day cannot continue to rely on scaling down extant components.
From 100 Billion to 7 Trillion Transistors
Simultaneously, semiconductor technology is advancing, which is creating limitless opportunities for computation. Modern 3nm processors and other intricate integrated circuits can already feature over 100 billion transistors.
A device could potentially accommodate approximately 7 trillion transistors within an area that is comparable to that of a modern semiconductor if the forecast for achieving 0.2nm technology by 2042 is realized. The capabilities of computing systems could be fundamentally altered by such an increase in component density.
Massive parallelism is a contributing factor to performance growth, in addition to the increase in the operational frequency of individual processors. Modern processors are capable of incorporating a significant number of computing cores and specialized accelerators onto a single die. This increase in computational density has become a fundamental component of modern digital systems, large-scale data processing, and artificial intelligence.
Krasnikov’s evaluation indicates that computing systems could achieve an approximate one millionfold increase in performance by the 2040s.
The Race to 28 nm and Russia
In light of this, Russia’s challenge appears to be particularly challenging. The Russian industry must first rebuild and establish the technological foundation necessary for substantially more mature process technologies, despite the fact that the global semiconductor industry is already transitioning to processes below 2nm.
However, 28 nm continues to be a critical milestone. At this level of technology, the production of a wide variety of modern electronics, such as processors, controllers, networking components, and specialized computational devices, would be feasible.
Krasnikov underscored that stable funding is the main prerequisite for attaining the Russian scenario. The construction of a semiconductor fabrication plant of the future could necessitate over one trillion rubles. However, the issue would not be resolved by just building the fab. Simultaneously, Russia would require infrastructure to manufacture chemical components, wafers, photomasks, ultra-pure materials, and other essential manufacturing inputs.
For this reason, the issue of Russian 28nm technology is not merely a matter of building a single factory. The issue at hand is the establishment of a comprehensive national semiconductor ecosystem.
Under a favorable scenario, according to the head of the Russian Academy of Sciences, Russia could achieve 28 nm technology by 2030–2031, move toward 14nm around 2033, and potentially approach 2nm by 2040. The feasibility of this timeline will be contingent upon the stability of government programs, the scale of investment, and the capacity of the Russian industry to simultaneously develop semiconductor production technologies, materials, and manufacturing equipment.