Intel made public on December 9 significant technological advancements that sustain an abundant supply of innovations for the organisation’s forthcoming process roadmap, highlighting the ongoing development and progression of Moore’s Law. Intel researchers demonstrated breakthroughs in 3D stacked CMOS (complementary metal oxide semiconductor) transistors with backside power and direct backside connections at the 2023 IEEE International Electron Devices Meeting (IEDM). Additionally, the organisation disclosed scaling strategies for recent advances in R&D concerning backside power delivery, including implementing backside contacts. It was also the first to demonstrate successful large-scale 3D monolithic integration of silicon transistors with gallium nitride (GaN) transistors on the same 300-millimetre (mm) wafer rather than on a package.
Continuing innovation is more critical than ever as Intel enters the Angstrom Era and considers expanding beyond five nodes in four years, according to Sanjay Natarajan, senior vice president and general manager of Components Research at Intel. He adds that Intel is presenting its advancements in research that support Moore’s Law at IEDM 2023, demonstrating its capability to deliver cutting-edge technologies that facilitate increased scalability and efficient power distribution for forthcoming mobile computing generations.
Scaling transistors and increasing backside power are crucial in addressing the escalating need for more potent computation. Intel release says it consistently satisfies this computational demand annually, showcasing that its advancements will persist in driving the semiconductor industry and serve as the bedrock of Moore’s Law. Intel’s Components Research group consistently pushes the boundaries of engineering by stacking transistors, advancing backside power to enable further transistor scaling and enhanced performance, and demonstrating that transistors made of different materials can be integrated on the same wafer, adds the release.
Components Research originated recent process technology roadmap announcements that emphasise the company’s innovation in continued scaling, such as Foveros Direct, glass substrates for advanced packaging, and PowerVia backside power. These products are anticipated to enter production this decade.
Intel says its Components Research demonstrated its dedication to developing novel techniques for multiplying the number of transistors on silicon while simultaneously improving performance at IEDM 2023. Researchers have identified vital R&D domains essential for scalability through efficiently stacking transistors. Combined with backside power and backside contacts, these will represent significant technological advances in transistor architecture. In addition to implementing innovative 2D channel materials and enhancing backside power delivery, Intel strives to extend Moore’s Law to one trillion transistors per package by 2030, as per the release.
Intel’s 3D-stacked CMOS transistor design incorporates backside power and contact
An industry first is demonstrated by Intel’s most recent transistor research at IEDM 2023: the capacity to vertically arrange complementary field effect transistors (CFET) with a scaled gate pitch of sixty nanometers (nm). This enables performance and area efficiency gains through the stacking of transistors. Additionally, backside power and direct posterior contacts are incorporated. This achievement highlights Intel’s dominant position in gate-all-around transistors and demonstrates the organisation’s capacity for innovation beyond RibbonFET, thereby establishing a competitive edge.
Integration of CMOS Transistors in 3D
An industry first is demonstrated by Intel’s most recent transistor research at IEDM 2023: the capacity to vertically arrange complementary field effect transistors (CFET) with a scaled gate pitch of sixty nanometers (nm). This achievement highlights Intel’s dominant position in gate-all-around transistors and its capacity for innovation that extends beyond RibbonFET, thereby establishing a competitive edge.
In four years, Intel identified critical R&D areas required to sustain transistor scaling with backside power delivery, surpassing five nodes, says the release.
In 2024, Intel will put into production PowerVia, the first implementation of backside power delivery. Components Research identified avenues for expanding and scaling backside power delivery beyond PowerVia and the critical process advancements necessary to make these goals a reality. Furthermore, reverse contacts and other innovative vertical interconnects facilitate space-efficient device stacking.
Integrate silicon and GaN transistors on a single 300 mm wafer
Intel prioritised performance enhancements and establishing a feasible trajectory towards 300 mm GaN-on-silicon substrates during IEDM 2022. The organisation is achieving progress in the integration of silicon and GaN processes this year. Intel has effectively showcased “DrGaN,” a large-scale integrated circuit solution renowned for its exceptional performance and ability to deliver power. Intel researchers have demonstrated for the first time that this technology operates effectively and can potentially enable power delivery solutions that can meet the increasing power density and efficiency requirements of future computation.
2D transistor R&D in preparation for future Moore’s Law scaling
Transition metal dichalcogenide (TMD) two-dimensional (2D) channel materials present a distinctive prospect for fabricating scaled transistors with physical gate lengths reduced to 10nm. Intel intends to showcase prototypes of high-mobility TMD transistors at IEDM 2023. These transistors are designed for NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor), which are fundamental components of CMOS. Additionally, Intel will showcase the first gate-all-around (GAA) 2D TMD PMOS transistor and a 2D transistor fabricated on a 300 mm wafer, both of which are firsts in the world.
