Russia is currently in the process of establishing a domestic technological framework for chiplet-based microelectronics. The objective is to address the constraints associated with advanced semiconductor manufacturing by using heterogeneous integration. The nation is establishing the groundwork for a new era of specialized computing systems and processors, with developments that include a registered tensor chiplet design and high-speed interconnect technologies that can achieve 112 Gbps.
In October 2026, the establishment of a Chiplets Working Group under Technical Committee 167 was a major milestone in the process of standardizing the technology. Russia is currently in the process of establishing its own ecosystem of chiplet designs, packaging technologies, and interconnect standards, while the United States and China are already implementing increasingly sophisticated multi-die architectures.
Chiplets Are Changing the Global Semiconductor Industry
The transition from monolithic processors to heterogeneous integration has become one of the defining developments in the global semiconductor industry. Chiplet technology divides a complex integrated circuit into multiple specialized dies connected through high-speed interfaces within a common package, rather than manufacturing an entire processor on a single silicon die.
A dedicated function, such as computing, memory control, input-output processing, or artificial intelligence acceleration, can be performed by each chiplet. It is crucial to note that semiconductor fabrication processes can be used to produce a variety of chiplets. Analog circuits, interfaces, and supporting components may depend on established production nodes, while high-performance computing components may use more sophisticated manufacturing technologies.
This method enables manufacturers to build increasing complex computing systems while simultaneously decreasing their reliance on the most advanced lithography processes. Chiplet technology provides an alternative approach to improving processor performance and expanding domestic design capabilities in Russia, where access to cutting-edge semiconductor manufacturing equipment remains restricted.
Intel, AMD, and China Are Advancing Chiplet Architectures
The international semiconductor industry has already progressed beyond the implementation of experimental chiplets. From 2019 onward, AMD contributed to the widespread adoption of the architecture by means of its Ryzen and EPYC processor families. Later the Instinct MI300 accelerator family demonstrated the potential of integrating high-bandwidth memory with CPU and GPU components in sophisticated heterogeneous packages.
Intel has aimed to achieve an even greater level of integration. The Ponte Vecchio data center GPU is a combination of 47 chiplets that use advanced packaging technologies, such as EMIB and Foveros. Vertically integrated chiplet architectures are also implemented in the Meteor Lake processors of the company, which illustrates the integration of various functional components into a single processor module.
The Universal Chiplet Interconnect Express (UCIe) standard is an important development that serves as the foundation of this ecosystem. It establishes standardized specifications for the physical interconnects and communication between chiplets that have been developed by various manufacturers.
With the release of UCIe 3.0 in August 2025, the supported data rates were increased to 48 and 64 GT/s per lane, and the link management and bandwidth flexibility were improved. These developments are necessary for guaranteeing that chiplets from various suppliers can communicate consistently within intricate semiconductor packages.
TSMC, a Taiwanese company, is also improving its advanced packaging capabilities by using its CoWoS platform. The company has gradually expanded the dimensions of silicon interposers, which has allowed for the creation of more complex and expansive multi-die configurations.
China is implementing its own strategy through Loongson. The 3C6000 server processor family is comprised of 16-core chiplets that are produced using a 12-nm process. Configurations can be scaled up to 64 cores. It is expected that the upcoming 3D7000 family will further broaden this approach by incorporating more sophisticated manufacturing technologies and larger chiplets.
These developments demonstrate that chiplet technology is becoming a more widespread architecture for high-performance computation, rather than merely an alternative processor design.
Russia Establishes a Domestic Chiplet Ecosystem
Russia’s efforts are being realized across multiple semiconductor design organizations, research institutes, and packaging facilities. The Chiplets Working Group, which was established on October 21, 2026, under Subcommittee 3, Trusted Electronic Component Base, of Technical Committee 167, serves as an institutional framework for the coordination of these activities.
Nevertheless, the semiconductor industry of the nation is already establishing a technological foundation that is more significant.
In collaboration with the Zelenograd Nanotechnology Center (ZNTC), the Research Institute NIIMA Progress is conducting research on the chiplet-based assembly of electronic components. The focus of its research is on applications that prioritize performance, reliability, and power efficiency, such as transceiver modules for active electronically scanned array (AESA) radar systems and compact telematics equipment.
ZNTC is also in the process of preparing a silicon interposer for a five-die multi-chip assembly. The current assembly and testing system is capable of producing up to 200,000 microchips per month and is compatible with PBGA, FC-BGA, and HFCBGA packaging technologies.
These capabilities establish an industrial foundation for the creation of more advanced heterogeneous semiconductor products.
NIISI Improves High-Speed Interconnect Technology
One of the most important challenges in chiplet development is the ability to transfer enormous quantities of data between individual dies without introducing excessive latency or power consumption.
The Kurchatov Institute’s Research Institute for System Studies (NIISI) is addressing this issue by advancing high-speed interconnect technologies.
The institute has successfully demonstrated the production of 25 Gbps transceivers using a 28-nm process. The development roadmap for this product includes the progression toward 112 Gbps PAM4 interfaces with more sophisticated processes, as well as interconnect speeds of up to 56 Gbps using the same manufacturing technology.
Additionally, NIISI is collaborating with the Russian Federal Nuclear Center – VNIIEF to develop the SMPO inter-machine interconnect.
These technologies have the potential to serve as critical building elements for future multi-chip processors, particularly in applications where multiple computing dies must function as a unified system.
In the interim, the Modul Scientific and Technical Center has advanced its NMC3–NMC6 family of neuromatrix computing cores. The NMC5 architecture of the system includes a chiplet-compatible interface that is designed to facilitate inference operations that involve large language models.
This offers a possible method for the integration of specialized artificial intelligence accelerators into heterogeneous computing platforms.
Tensor Chiplet Receives Russian Patent Registration
The registration of a tensor chiplet topology by Rospatent is a particularly noteworthy development.
The design concerns a specialised 28-nm semiconductor die measuring approximately 30 square millimetres, incorporating ten metallisation layers and flip-chip mounting technology. It is designed to expedite matrix operations that are employed in artificial intelligence applications and neural networks.
The registered topology is intended for integration into a heterogeneous system-in-package architecture, enabling specialized compute components to operate in conjunction with other processor and interface dies.
The rights holder is the Russian Federation, represented by the Foundation for Advanced Research (FPI).
The registration is important because it establishes a documented domestic engineering design that has the potential to be licensed to Russian semiconductor design centers. It also illustrates that the country’s chiplet development program is expanding beyond general research to include specific functional semiconductor architectures.
Nevertheless, patent registration should not be confused with commercial production or demonstrated performance. Fabrication, packaging, validation, and integration with compatible components will determine industrial deployment.
Advanced Packaging and Thermal Management
Another challenge associated with chiplet architectures is heat dissipation. The thermal density increases as more computing dies are integrated into increasingly compact packages, which complicates conventional cooling methods.
To resolve this issue, Russian organizations are investigating alternative packaging technologies.
Rosatom Quantum Technologies is in the process of creating silicon-free interposers with contact pitches of up to 10 micrometers. In the interim, NPO Energomodul is developing thermal interposers that are composed of silicon carbide and diamond.
These materials possess properties that could assist in the regulation of heat in densely integrated semiconductor packages.
The development of such technologies is crucial because the performance of chiplets is contingent upon the computing capabilities of individual dies, as well as the capacity to maintain stable operating temperatures and reliable electrical connections.
Why Russia Wants Its Own Chiplet Standards
The Chiplets Working Group was established to address one of the most significant challenges that Russia’s emerging ecosystem is currently encountering: compatibility.
The components of individual chiplets developed by various organizations must adhere to common regulations regarding thermal requirements, data-transfer protocols, packaging dimensions, electrical interfaces, and testing procedures.
Independently developed semiconductor dies are unable to be integrated into a functional system in the absence of standardization.
An institutional platform for addressing this challenge is provided by Technical Committee 167, which establishes standards for trusted hardware and software systems used in Russia’s critical information infrastructure. Trusted electronic components are the primary focus of Subcommittee 3.
Consequently, the objective of the new working group is to establish common technical requirements that are comparable in nature to international frameworks like UCIe and 3Dblox.
In conclusion,
The chiplet program in Russia is an effort to establish a more distributed semiconductor ecosystem by integrating specialized design centers, fabrication facilities, and advanced packaging organizations. Concrete starting points are provided by the registered tensor chiplet, NIISI’s high-speed interconnect roadmap, and ZNTC’s multi-die assembly capabilities. However, the definitive evaluation will be whether these advancements can be transformed into semiconductor products that are compatible, commercially deployable, and capable of being manufactured.